1. Field of the Invention
The present invention relates to an interface circuit and method for coupling between a memory device and processing circuitry
2. Description of the Prior Art
In a data processing apparatus, such as a pipelined data processing apparatus, a series of serially connected stages are formed. The processing circuitry of each processing stage is responsive to input signals received from preceding processing stages in the pipeline or from elsewhere and generates output signals. Between each stage of the pipeline is provided a signal capture element such as a latch or a sense amplifier into which one or more signal values are stored. The latch receives the input signals, stores the input signal value and presents this stored value on its output in response to a clock signal provided thereto.
In order for the latch to reliably store the input signals provided at its input, it is necessary for the input signal to achieve a particular voltage level representative of a value to be stored at a time which is no later than a predetermined period prior to the clock signal being provided to the latch (known as the set-up period) and for this voltage level to be maintained for a predetermined period following the provision of the clock signal (known as the hold period).
However, in the event that the input signals provided to the latch transitions in the set-up or hold period then metastability can occur. A consequence of this is that the output provided by the latch does not make a clean transition between logic levels but instead achieves a value somewhere therebetween, known as a metastable voltage. Typically, the metastable voltage is a level approximately midway between the valid logic level voltages.
Metastability is typically avoided by ensuring that the input signals only transition outside of the set-up and hold periods. This ensures that the input signals can be cleanly sampled by the latch.
However, in order to attempt to improve the performance of data processing apparatuses, it is known to increase the speed at which the processing stages are driven by increasing the clock rate until the slowest processing stage in the pipelined processor is unable to keep pace. Also, in situations where it is desired to reduce the power consumption of the data processing apparatus, it is known to reduce the operating voltage up to the point at which the slowest processing stage is no longer to keep pace. In both of these situations it is no longer possible to ensure that the signal transitions do not occur within the set-up and hold periods and metastability can occur. An example of an integrated circuit arranged to operate under such conditions is described in commonly owned U.S. Pat. No. 7,278,080, the entire contents of which are hereby incorporated by reference.
A consequence of such metastability is that erroneous data values may be generated. In extreme cases, erroneous control signals may also be generated which may cause valid data to be corrupted. For example, should metastability occur whilst performing an access to a memory device then a corruption of the internal state of the memory may occur.
In order to avoid metastability causing corruption of the internal state of the memory device, write accesses to the memory device may be placed in a write queue. The write accesses are then only allowed to occur once a system level validation process has confirmed that the signals associated with the write access are valid and that no metastability in those signals exists.
However, placing read accesses to the memory in a read queue in an equivalent manner to write accesses would introduce delays when retrieving data. Introducing such delays would adversely reduce the overall performance of the data processing apparatus to unacceptable levels, due to the sensitivity of processing throughput on load latency.
Nevertheless, using signals produced directly by logic which may be metastable could lead to metastable signals in turn being provided to an address decoder used to access the memory. Commonly owned U.S. Pat. No. 7,263,015, the entire contents of which are hereby incorporated by reference, describes latch circuitry for read address signals which produces two outputs for input to the address decoder which in normal operation should be the inverse of each other. In such cases, the decoder uses one of the outputs to select the relevant wordline. However, in the event of metastability arising, the latch circuitry generates the two outputs at the same logic level, causing the address decoder to not activate any wordlines. As a consequence, no corruption in the state stored in the memory can result due to metastability in the read address input.
However, another problem that can arise is that one or more signals used to identify whether a write operation or a read operation should be performed may also suffer from metastability problems. In particular, arbitration techniques are typically provided in order to deal with the occurrence of concurrent read and write access over the common buses, with read accesses being given priority over write accesses. Accordingly, read accesses are performed in preference, with write accesses being placed in the write buffer and postponed until after the write access is confirmed to be error free and no read accesses are outstanding.
Often such arbitration techniques make use of a signal generated by the processing circuitry to indicate whether a read access is to take place. If such a signal is metastable then this may cause metastable signals to be used directly in the arbitration of data accesses. This in turn can result in many different types of errors occurring when accessing data. In an extreme case, these errors may cause the data to become corrupted. It will be appreciated that corrupting data is undesirable at the best of times; however, data corruption due to metastability is particularly disadvantageous since it will be almost impossible to determine the corruption occurred since it is extremely unlikely that the status of the signals causing the corruption can be determined.
Commonly owned U.S. patent application Ser. Nos. 11/121,309 and 12/068,598, the entire contents of which are hereby incorporated by reference, describe a prediction mechanism, where an indication that an instruction is to be processed by the pipelined data processing apparatus is received and a memory access prediction signal is then generated. The memory access prediction signal has a value indicative of whether or not the instruction is likely to cause a read access from a memory. Hence, an indication is provided when the instruction is likely to cause a read access. A predicted memory access control signal is generated from the memory access prediction signal.
The predicted memory access control signal is generated in a way which prevents any metastability being present in that signal. This is achieved by the predicted memory access control signal achieving and maintaining a valid logic level for at least a sampling period. A read access can then be initiated in the event that it is predicted that a read access is likely to occur.
In this way, a signal used to initiate a read access can be generated in a way which ensures that it will have no metastability. This is possible because that signal is merely a prediction signal rather than the decoded instruction itself and, hence, can be generated much earlier in the pipeline. Because the prediction signal is generated much earlier in the pipeline, it can be ensured that the signal used to cause the memory access has no metastability.
Whilst the above approach removes the possibility that metastable signals are used directly in the arbitration of data accesses, it requires the use of a prediction signal, which will hence require the need for correction mechanisms in the event that the prediction later proves to be wrong, thereby increasing complexity of the data processing apparatus. Accordingly it would be desirable to provide an improved technique for avoiding metastable signals being used in the arbitration of data accesses in a way which could corrupt state of the memory device.